GPIO max current

[throstur62]

Hi,
A simple question, that I can't find any clear answare for:
What is the maximum current allowed from a GPIO pin?

I also se different numbers for the maximum allowed current for the 3v3 pin (pin 1). Anyone clear over what the maximum is.

Regards
TJ

[jbeale]

First, some terminology: normally "GPIO pin" refers to general-purpose input/output pins from a CPU, microcontroller or SoC, but on the RPi board, the issue is confused by the fact that among the 13x2 "GPIO Header" pins are two actual power rails, 3V3 and 5V.

The data input/output pins are limited by what the SoC on-chip drivers can source and sink, which is actually configurable:

GPIO input hysteresis (Schmitt trigger) can be on or off, output slew rate can be fast or limited, and source and sink current is configurable from 2 mA up to 16 mA. Note that chipset GPIO pins 0-27 are in the same block and these properties are set per block, not per pin. See GPIO Datasheet Addendum - GPIO Pads Control. Particular attention should be applied to the note regarding SSO (Simultaneous Switching Outputs): to avoid interference, driving currents should be kept as low as possible.
... from http://elinux.org/Rpi_Low-level_periphe ... .28GPIO.29

The current output from the 3V3 rail should be limited to 50 mA (same page as above). The current from the 5V rail is up to your judgement, but you'll be limited by the 750 mA power input fuse that also supplies everything on the board including the USB devices. Although, note you can actually power the board by +5V INPUT on this pin- but then you are not protected by the fuse, or the power diode overvoltage crowbar on the normal microUSB power input.

[throstur62]

Thanks for your replay jbeale. The link was very usefull. However it confuses me also as the child school equation V = IR is burned in my head.
When a GPI pin is configured as output, it can be looked at as a voltage source but not current source. Therefore teh outside resitance controls the current via the pin. The current can not be controlled programaticly in this case.
So does this current-configuratoin apply only to the pins when configured as input pins?
In that case I don't understand this either as you can configure those for example with a pullup-resistor and then that resistor is controlling the current (when the outside switch is not shunting the input pin).

The only thing I understand here is the hysterisis rise and fall.

[jbeale]

I don't actually know what the configurable drive current configures, this is intended to be a digital output and not a current source/sink. It may be that you get a configurable "current boost" for a short time during transition from 0-1 or 1-0 to increase switching speed into a capacitive load, but the static DC current delivered after that remains at some fixed, probably low level.

The outputs are designed to deliver 0V or 3V3 levels into CMOS inputs (high input impedance) and they can source or sink at least 3 mA into a resistive load (that is, resistors as low as 1k ohm should be OK). Beyond that, I do not know. I vaguely recall that one person experimentally determined that R-Pi GPIO outputs can deliver about 30 mA into a LED load, with voltage sagging to 2V or below, but I haven't tried that and I would experiment with caution.

Or for a better answer, see: http://www.raspberrypi.org/phpBB3/viewt ... 48#p131518

[Grumpy Mike]

I vaguely recall that one person experimentally determined that R-Pi GPIO outputs can deliver about 30 mA into a LED load, with voltage sagging to 2V or below,

That sort of current is likely to damage the GPIO pin. The damage might not show up immediately but it is damaged and might fail much sooner than normal. It is like saying I smoke 100 a day and I am still alive. Yes but for how long?

Also that is not saying you can do that for every pin.
Unfortunately the full data sheet has nothing to say about absolute maximum pin currents, it is a tricky thing to characteristic anyway. So just stick to the figures I gave in the linked thread above.

[rgh]

GPIO input hysteresis (Schmitt trigger) can be on or off, output slew rate can be fast or limited, and source and sink current is configurable from 2 mA up to 16 mA. Note that chipset GPIO pins 0-27 are in the same block and these properties are set per block, not per pin. See GPIO Datasheet Addendum - GPIO Pads Control. Particular attention should be applied to the note regarding SSO (Simultaneous Switching Outputs): to avoid interference, driving currents should be kept as low as possible.
... from http://elinux.org/Rpi_Low-level_periphe ... .28GPIO.29

Does anyone have a copy of that "GPIO Datasheet Addendum - GPIO Pads Control"? The link on the wiki is broken - target document has been deleted.. Thanks.

[Gert van Loo]

That document had a major error in it. I accidentally deleted it instead of putting up a new version.
The new one is correct and also has A LOT more text on how to interpret the data.

http://www.scribd.com/doc/101830961/GPIO-Pads-Control2

[Grumpy Mike]

Have you read this?
http://www.thebox.myzen.co.uk/Raspberry ... tputs.html
It tries to explain what it means.

I was just going to post it but Gert intervened before the post was finished. It was too big to post anyway.

[jojopi]

http://www.scribd.com/doc/101830961/GPIO-Pads-Control2:
V_IL = 0.8V means that if the output is Low it will be <= 0.8V

Should that not be V_OL? Or are we saying that the drive strength is the current at which the noise margin will be zero?

Also, the document implies that we might want to decrease the drive strength if the load is capacitive. But is that not also a case where we might sometimes need a higher drive strength than suggested by the static discipline, in order to maintain acceptable rise/fall times?

(I have updated both links that I could find in the wiki.)

[andig2]

I'd like to add the question of what a safe voltage is for the 3.3V raspi GPIOs. How much is too much?

[joan]

I'd like to add the question of what a safe voltage is for the 3.3V raspi GPIOs. How much is too much?

Mine shows 3.63V on the 3.3V pin (no load other than the Pi).

[jojopi]

Mine shows 3.63V on the 3.3V pin (no load other than the Pi).

Either the meter is wrong, or your RG2 is well out of spec. It should be 3.235V to 3.365V, according to the OnSemi data sheet.

Anyway, I think the question was what voltages will the GPIO pins tolerate. The answer to that is 0V to 3.3V. If you go more than a small fraction of a volt outside that range, the SoC's ESD clamping diodes will begin to conduct. Unlike on some 8bit microcontrollers, the diodes in the BCM2835 are not rated for any continuous current. So there is a risk of damage even at 3.6V.

[MohitBagur]

What is the max current I can draw from the 5v output in the GPIO?

[joan]

What is the max current I can draw from the 5v output in the GPIO?

If you are feeding the Pi via the microUSB socket the overall current is limited by the polyfuses of 1 or 2 amps (depending on Pi model).

You can draw the residue left after powering the Pi and its connected peripherals.

[boyoh]

You will not get any clear answers to your to your question, all have different answers
This as been asked since the first Pi came out, It is said the GPIO out/put will let you
draw a current of 16ma, but no more than 50ma from the Pi at a voltage of 3.3v+,

My advice is use if your project is voltage and current demanding , is use buffer stages
Voltge and current amplifiers , Using the Pi GPIO's as signal switching of Transistors
Opto Isolators Relays for higher current and voltage levels. Any feed back to the Pi in/puts
I suggest you use opto isolators

[franekz]

but no more than 50ma from the Pi at a voltage of 3.3v+,

Which is not the truth on the new PIs

[jamesh]

but no more than 50ma from the Pi at a voltage of 3.3v+,

Which is not the truth on the new PIs

You sure? I don't think the SoC GPIO output specs haven't changed (I could be wrong), have you a reason for believing this?

[6by9]

A 2 year old thread necro. Ho hum.

but no more than 50ma from the Pi at a voltage of 3.3v+,

Which is not the truth on the new PIs

You sure? I don't think the SoC GPIO output specs haven't changed (I could be wrong), have you a reason for believing this?

No, nothing has changed on the SoC GPIO output spec. Max 16mA per pin, and 50mA per bank.

What has changed is the power available from the 3.3V rail due to the use of an external SMPS on Pi2 and 3, and somewhat on the 5V rail with the replacement of the polyfuse.

[gordon77]

Where does' 50mA per bank' come from?

[Gert van Loo]

Me.

[gordon77]

Me.

Anymore details eg what's a bank?

[piras77]

Me.

Is there some reference for this? It appears to me quite a bit too little. The resulting dissipation would be approx. something about 25mW (at dU 500mV),

And, even though it is no contradiction, why did you write: "If you load each pin with 16mA the total current is 272mA. The 3V3 supply will collapse under that!" if 50mA are already the limit?

[6by9]

Me.

Anymore details eg what's a bank?

I thought this was in the peripheral spec, but can't see it on a quick search.
GPIOs 0-27 = bank 0
GPIOs 28-45 = bank 1
GPIOs 46-53 = bank 2

*edit* It's in the Compute Module datasheet, section 9.1.
The other thing is that each bank can be run from a different supply rail, so on most Pi's bank 2 is 1V8, whilst the others are 3V3.

[6by9]

Me.

Is there some reference for this? It appears to me quite a bit too little. The resulting dissipation would be approx. something about 25mW (at dU 500mV),

On what basis is that too little other than you want to draw bigger currents?
25mW on a device that is consuming <1W (*) is 2.5% just on driving your GPIOs rather than doing any processing. What a waste.

And, even though it is no contradiction, why did you write: "If you load each pin with 16mA the total current is 272mA. The 3V3 supply will collapse under that!" if 50mA are already the limit?

I suspect the 50mA isn't a hard limit enforced in the hardware, it's the point where you'll be creating issues.
Within the SoC you're routing power from balls underneath to each block. How big do you make the power rails in each case? If you want 200mA you have to put the copper in there to carry it, and that costs (mainly in area).
Also the power supply has to be able to supply that much current at that particular voltage. The headroom on the 3.3V SMPS within the BCM2835 isn't huge, hence why Gert says the 3V3 power rail will collapse. There is some more headroom on the Pi2 and Pi3 as they use an external SMPS, but it still isn't 100's mA.

Seeing as Gert was one of the hardware engineers who designed this chip, take what he says as sound engineering advice based on the design decisions made for the SoC.

(*) approx the original design power dissipation - IIRC the full camcorder use case was around 700mW.

[gordon77]

"Seeing as Gert was one of the hardware engineers who designed this chip, take what he says as sound engineering advice based on the design decisions made for the SoC. "
Happy to do that, just trying to understand the details