2nd SPI port usable?

[dBC]

I've come across several references that say the 2nd SPI pins haven't been run from the Broadcom chip to the IO header, and so are pretty much unusable. For example:

http://elinux.org/RPi_BCM2835_GPIOs

But then I came across this product, that clearly states it breaks out both SPI buses:

http://www.bitwizard.nl/catalog/product ... ucts_id=69

So now I'm confused

[Gert van Loo]

I have found no schematics of that products but all I can think of is that they bring out BOTH SPI chip selects of the ONE SPI interface.

[gordon@drogon.net]

I've come across several references that say the 2nd SPI pins haven't been run from the Broadcom chip to the IO header, and so are pretty much unusable. For example:

http://elinux.org/RPi_BCM2835_GPIOs

But then I came across this product, that clearly states it breaks out both SPI buses:

http://www.bitwizard.nl/catalog/product ... ucts_id=69

So now I'm confused

The Broadcom SoC has three independant SPI interfaces, however only one of these is brought out to the GPIO connector, and that one SPI interface has 2 Chip enable lines.

So the Raspberry Pi (as a system) has one SPI bus with 2 chip enable lines. These are independantly usable. For example on the Gertboard there are 2 SPI peripherals connected to the same bus, but each one has one of the 2 available CE lines.

So you can easilly connect 2 different SPI devices to the Pi.

That breakout board presumably is a PCB with two little 6-pin connectors, and I'm presuming each connector has one of the 2 CE lines brought out to it.

SPI typically has a clock line, a master out (slave in) data line and a master in (slave out) data line. These 3 signals lines are connected to every SPI peripheral, then each peripheral gets one chip enable line. The Pi has 2 CE lines, so can talk directly to 2 different SPI peripherals.

-Gordon

[dBC]

Thanks for the clarification. I can see my original post kinda' confused ports with buses.

So I assume the two devices I see in /dev: /dev/spidev0.0 /dev/spidev0.1

correspond to the two ports that are available (i.e the two chip enable lines)?

If I can guarantee that the RPi will be the only SPI master on the bus, can I leave the two "official" chip enable lines disconnected, and run my own via GPIO pins? Then my software will be responsible for asserting a particular chip enable (via GPIO) before it issues any transactions, and de-asserting it afterwards. Presumably I'm then limited only by the number of GPIO pins I have available? And I assume it doesn't matter which of the above two devices I use, since they'll both results in the same actions on the 3 signals that matter (CLK, DI, DO)?

[Gert van Loo]

Yes, that is the way to go if you want more devices.
But... you can still use the two SPI chips selects as there is a mode where neither of them is asserted.
So you can use the default two first and then switch to using SW controlled Chip select pins.
The penalty is a bit more complex SW but the gain is that you have two 'fast ' devices where your CS is done for you.

[dBC]

Even better than I imagined, thanks.

[HariGanti]

Gert and Gordon, how can I use SPI with neither CS line selected? I have far more SPI devices than CS lines available (or SPI busses for that matter), and I'd like to be able to use the built in CS lines, and add more as necessary. I am also using the wiringPiSPI library for SPI communication. If possible, it would be nice to have two SPI devices where I don't need extra function calls to pull a GPIO low, then begin SPI communication, then drive it high again.

Thanks!

[Gert van Loo]

..how can I use SPI with neither CS line selected? ...

I have not looked at the datasheet but I assume that would tell how to program the hardware in such a way that there is no CS.
But that would not help if that is not supported by the drivers. So in this case you have to look if the wiringPiSPI library supports a mode with no chip-select.

[HermannSW]

The Pi Zero has SPI0 with CE0 and CE1 enabling lines.
But it also has SPI1, the 1st line enables SPI, the 2nd enables SPI1 interface with 3 chip select lines:

Code: Select all

pi@raspberrypi:~ $ grep spi /boot/config.txt 
dtparam=spi=on
dtoverlay=spi1-3cs
pi@raspberrypi:~ $ 

After boot there are 5 SPI devices:

Code: Select all

pi@raspberrypi:~ $ ls -l /dev/spi*
crw-rw---- 1 root spi 153, 0 Sep 27 21:47 /dev/spidev0.0
crw-rw---- 1 root spi 153, 1 Sep 27 21:47 /dev/spidev0.1
crw-rw---- 1 root spi 153, 4 Sep 27 21:47 /dev/spidev1.0
crw-rw---- 1 root spi 153, 3 Sep 27 21:47 /dev/spidev1.1
crw-rw---- 1 root spi 153, 2 Sep 27 21:47 /dev/spidev1.2
pi@raspberrypi:~ $ 

A small 320x240 TFT display can be enabled on SPI1 with fbtft_driver using this command:

Code: Select all

pi@raspberrypi:~ $ sudo modprobe fbtft_device name=rpi-display gpios=reset:13,dc:26,led:27 rotate=90 cs=2 busnum=1
pi@raspberrypi:~ $ 

This is tail of dmesg:

Code: Select all

$ dmesg
...
[   48.369622] Adding 102396k swap on /var/swap.  Priority:-1 extents:1 across:102396k SSFS
[  271.461035] fbtft: module is from the staging directory, the quality is unknown, you have been warned.
[  271.467496] fbtft_device: module is from the staging directory, the quality is unknown, you have been warned.
[  271.468908] spidev spi0.0: spidev spi0.0 500kHz 8 bits mode=0x00
[  271.468924] spidev spi0.1: spidev spi0.1 500kHz 8 bits mode=0x00
[  271.468936] spidev spi1.2: spidev spi1.2 500kHz 8 bits mode=0x00
[  271.468945] spidev spi1.1: spidev spi1.1 500kHz 8 bits mode=0x00
[  271.468954] spidev spi1.0: spidev spi1.0 500kHz 8 bits mode=0x00
[  271.469009] bcm2708_fb soc:fb: soc:fb id=-1 pdata? no
[  271.469046] spidev spi1.2: Deleting spi1.2
[  271.482161] fbtft_device: GPIOS used by 'rpi-display':
[  271.482175] fbtft_device: 'reset' = GPIO13
[  271.482180] fbtft_device: 'dc' = GPIO26
[  271.482183] fbtft_device: 'led' = GPIO27
[  271.482200] spidev spi0.0: spidev spi0.0 500kHz 8 bits mode=0x00
[  271.482209] spidev spi0.1: spidev spi0.1 500kHz 8 bits mode=0x00
[  271.482220] spidev spi1.1: spidev spi1.1 500kHz 8 bits mode=0x00
[  271.482238] spidev spi1.0: spidev spi1.0 500kHz 8 bits mode=0x00
[  271.482248] spi spi1.2: fb_ili9341 spi1.2 32000kHz 8 bits mode=0x00
[  271.588502] fb_ili9341: module is from the staging directory, the quality is unknown, you have been warned.
[  271.947044] graphics fb1: fb_ili9341 frame buffer, 320x240, 150 KiB video memory, 16 KiB DMA buffer memory, fps=20, spi1.2 at 32 MHz
pi@raspberrypi:~ $ 

SPI1 GPIOs from http://elinux.org/RPi_SPI#Hardware

Code: Select all

SPI1 (available only on 40-pins P1 header)

SPI Function	Header Pin	Broadcom Pin Name	Broadcom Pin Function
MOSI	P1-38	GPIO20	SPI1_MOSI
MISO	P1-35	GPIO19	SPI1_MISO
SCLK	P1-40	GPIO21	SPI1_SCLK
CE0	P1-12	GPIO18	SPI1_CE0_N
CE1	P1-11	GPIO17	SPI1_CE1_N
CE2	P1-36	GPIO16	SPI1_CE2_N

Hermann.

Code: Select all

pi@raspberrypi:~ $ tail --bytes 153600 giraffe.565 > /dev/fb1
pi@raspberrypi:~ $