Accessing SCR in Monitor mode (Pi 2)

[vsiles]

Hi, I'm playing with the secure "Trustzone" world of the Pi 2.
Thanks to dom http://www.raspberrypi.org/forums/viewt ... 74#p697474 I managed to boot in several modes (set kernel_old=1 in config.txt, link his code at 0x0 and your kernel at 0x8000), but a really weird situation is happening.

In his boot code http://pastebin.com/rgGgBuTN, here is what happens:
- We start at 0x0 in svc / secure mode.
- After a few instructions, we jump into monitor secure mode with

Code: Select all

 smc #0 

- In the _secure_monitor, we set SCR.NS to 1, and we exit with a return from exception

Code: Select all

movs pc, lr

- back from the _secure_monitor, we are now in svc / non secure mode

Ultimately, I want to jump to my kernel code at 0x8000 (line 116) in svc / secure mode, but keeping SCR.NS to 0 in the _secure_monitor makes the board hangs.

Code: Select all

 
        bic     r1, r1, #0x4e                   @ clear IRQ, FIQ, EA, nET bits
        orr     r1, r1, #0x30                   @ enable AW, FW bits   <<< 0x30 instead of 0x31 so that NS is still 0
        orr     r1, r1, #0x100                  @ allow HVC instruction

        mcr     p15, 0, r1, c1, c1, 0           @ write SCR (without NS bit set)

I don't know exactly where it crashes, but I expect it to be at the return from _secure_monitor since setting SCR.NS in a second time works perfectly fine.

Code: Select all

 
        bic     r1, r1, #0x4e                   @ clear IRQ, FIQ, EA, nET bits
        orr     r1, r1, #0x30                   @ enable AW, FW bits   <<< 0x30 instead of 0x31 so that NS is still 0
        orr     r1, r1, #0x100                  @ allow HVC instruction

        mcr     p15, 0, r1, c1, c1, 0           @ write SCR (without NS bit set)
        orr     r1, r1, #0x1
        mcr     p15, 0, r1, c1, c1, 0           @ write SCR (with NS bit set)

If I replace the return from the monitor with "bx lr" instead of "movs pc, lr", I will successfully reach 0x8000 in monitor / non secure mode. But again, If I try to keep SCR.NS to 0, the board hangs.

The really disturbing thing is that I can switch SCR.NS from 0 to 1 without any trouble as soon as I jumped at 0x8000. I really don't understand why I can't change it back and forth before the jump at line 116.

[mimi123]

Hi, I'm playing with the secure "Trustzone" world of the Pi 2.
Thanks to dom http://www.raspberrypi.org/forums/viewt ... 74#p697474 I managed to boot in several modes (set kernel_old=1 in config.txt, link his code at 0x0 and your kernel at 0x8000), but a really weird situation is happening.

In his boot code http://pastebin.com/rgGgBuTN, here is what happens:
- We start at 0x0 in svc / secure mode.
- After a few instructions, we jump into monitor secure mode with

Code: Select all

 smc #0 

- In the _secure_monitor, we set SCR.NS to 1, and we exit with a return from exception

Code: Select all

movs pc, lr

- back from the _secure_monitor, we are now in svc / non secure mode

Ultimately, I want to jump to my kernel code at 0x8000 (line 116) in svc / secure mode, but keeping SCR.NS to 0 in the _secure_monitor makes the board hangs.

Code: Select all

 
        bic     r1, r1, #0x4e                   @ clear IRQ, FIQ, EA, nET bits
        orr     r1, r1, #0x30                   @ enable AW, FW bits   <<< 0x30 instead of 0x31 so that NS is still 0
        orr     r1, r1, #0x100                  @ allow HVC instruction

        mcr     p15, 0, r1, c1, c1, 0           @ write SCR (without NS bit set)

I don't know exactly where it crashes, but I expect it to be at the return from _secure_monitor since setting SCR.NS in a second time works perfectly fine.

Code: Select all

 
        bic     r1, r1, #0x4e                   @ clear IRQ, FIQ, EA, nET bits
        orr     r1, r1, #0x30                   @ enable AW, FW bits   <<< 0x30 instead of 0x31 so that NS is still 0
        orr     r1, r1, #0x100                  @ allow HVC instruction

        mcr     p15, 0, r1, c1, c1, 0           @ write SCR (without NS bit set)
        orr     r1, r1, #0x1
        mcr     p15, 0, r1, c1, c1, 0           @ write SCR (with NS bit set)

If I replace the return from the monitor with "bx lr" instead of "movs pc, lr", I will successfully reach 0x8000 in monitor / non secure mode. But again, If I try to keep SCR.NS to 0, the board hangs.

The really disturbing thing is that I can switch SCR.NS from 0 to 1 without any trouble as soon as I jumped at 0x8000. I really don't understand why I can't change it back and forth before the jump at line 116.

Try to go to secure mode after the jump

[vsiles]

Yes, going to secure mode after the jump works perfectly fine.
I just wonder why it doesn't work in the same way before the jump. I mean, only pc should have been updated by this jump, am I right ? Maybe it has to do with the fact that all of the cores are running before the jump ? (I am a total noob with smp / multiple cores)

[vsiles]

For the record, here is a fully detailed answer of the problem and how to solve it.

http://community.arm.com/message/25127

Summary: use ISB when switching SCR.NS to be sure to read the correct banked version of the CP15 register you want to access, and be careful not to access "non secure only" register in the secure world.

[EngineerN]

Hello @vsiles,

Did you have you code in any git repo ? I'm trying to explore the RPi TrustZone, and I struggle with the secure boot and moving from the secure to normal world.

Thank you in advance.

[vsiles]

Hi,
since Stephen Warren is working on fixing rpi2 usb/ethernet support in u-boot, I switched from my boot code to using u-boot, which already supports secure boot.

To boot in secure mode with u-boot, I needed to fix a couple of places in u-boot, but very little was actually necessary, it is mainly patches so that the code can compile. The really important one is https://github.com/vsiles/u-boot/commit ... f26f564765

You can find all of my patches at https://github.com/vsiles/u-boot. At the moment, I apply them on top of Stephen's tree (his rpi_dev branch), but this is bound to change when the main u-boot repo will be fixed.

[EngineerN]

Thank you very much for your repos !!
Which OSs do you run in the secure and the normal world ?

Thank you in advance

[vsiles]

At the moment I run my baremetal hobby OS, and we are not yet to the "both secure & normal world" things, but we aim to run android/ubuntu on the normal world... one day