This stuff is dealt with in a document called the ARM ARM. There's one for each iteration of the ARM. The latest is ARM v7 ARM, I think. Each version gets more complicated and unpleasant to read than the previous
The CPSR is the current program status register, and holds info like processor mode (User mode or the various privileged modes) and whether (fast)interrupts are enabled. This stuff used to be encoded within the PC (ARM v2, as described in that old book...).
Each exception mode (the privileged modes, other than System, ie. SVC, UND, ABT, IRQ, FIQ) which are entered from User mode when an exception occurs, such as an undefined instruction, or a hardware interrupt) has its own R13 (SP) and R14 (LR) registers. (FIQ also has its own R8-R12).
When, for example, an interrupt occurs, the processor switches to IRQ mode and jumps to memory location 0x00000018 which, hopefully, contains a branch to your interrupt handler code.
If that code uses R13 or R14 those will not be the User mode R13 and R14, but IRQ's R13 and R14 registers. So, you need to set IRQ's SP as well as User mode's. The only way to do that is to switch to IRQ mode, and then set SP.
This sort of thing is usually done on Reset, because you're in a privileged mode, from which you can set your SP and then switch to another privileged mode to set that
mode's SP and so on.
Finally you switch to the unprivileged User mode, and can only get back into a privileged mode through one of the aforementioned exceptions.
To change the CPSR (to change mode) a special instruction, msr, is used. The _c flag on CPSR means that only the "control" bits of the whole register will be changed. The IRQ and FIQ bits are specified so that interrupts don't occur while you're doing this.