I think I may have found a clue...
I downloaded the DSI-Tuner app from TI to see what it recommends. The CSRs it suggests aren't significantly different than what the sn65dsi83 driver is setting (though DSI-Tuner doesn't set the test-pattern-only registers).
However, it says the "LINE TIME (SYNC to SYNC) REQUIREMENT (us)" is 20.84 microseconds, which follows from the calculation that hactive + hfront_porch + hback_porch + hsync_len = (1024 + 260 + 480 + 320) = 2084 pixels clocks, and the clock speed is 100MHz.
From the manual for DSI-Tuner (
https://www.ti.com/lit/an/slla332b/slla ... 8142549274),
The video transfer is done on a line-by-line basis in the SN65DSI8x device. The rule of
thumb for the DSI data transfer using the SN65DSI8x devices is to match the line time
(Sync-to-Sync time) between the input and the output. It is also important to maintain the
data rate so as not to underflow or overflow the internal buffer. The SN65DSI85 supports
a programmable delay value to help maintain the data rate and the availability of data in
internal buffers. The delay value, also referred as “sync delay”, is used to delay the
outgoing data, up to 0xFF number of pixels, by programming the corresponding register
field. The sync delay value can be calculated based on the DSI input parameters and the
LVDS output requirements. It is important to program the sync delay value to a properly
calculated value for correct operation of the device.
When I measure the sync-to-sync time on the DSI lines, I see a sync period of 13.16 microseconds.
I wonder if what's happening here is that the DSI HSync/HFP/HBP are defaulting to some typical values, which are much shorter than the very long hsync parameters that this panel wants.
Is there a way to tweak the DSI hsync parameters? I don't see anything obvious in vc4_dsi.c, nor anything obviously setting the DSI timing parameters in sn65dsi83.c
