Eric Buddington
Posts: 15
Joined: Mon May 03, 2021 1:53 pm

When are PIO X/Y registers reset?

Mon Feb 12, 2024 2:52 pm

I'm trying to write correct code to preload a 32-bit value into the X register of a PIO that will have FIFOs joined as RX when running. I believe the normal way to do this is to put the value in the TX FIFO, then use pio_sm_exec() to move that to the X register. After that, I need to reconfigure the SM, at least to join the FIFOS.

My question is: are there any operations that I need to be careful of that would wipe my value from the X register? Writing SM_RESTART in the PIO CTL register clears a lot of internal state, but apparently not X, Y, or PC. The documentation of SM_RESTART don't mention them at all, so I assume it leaves them alone.

arg001
Posts: 605
Joined: Tue Jan 23, 2018 10:06 am

Re: When are PIO X/Y registers reset?

Mon Feb 12, 2024 5:03 pm

Eric Buddington wrote:
Mon Feb 12, 2024 2:52 pm
The documentation of SM_RESTART don't mention them at all, so I assume it leaves them alone.
Which version of the documentation are you looking at? In section 3.7 of the datasheet (page 372 of the PDF) it explicitly says that X,Y and OSR are not cleared (but ISR is cleared). That was there in the version that I happened to have open on my desktop (V2.2); your question prompted me to check if I was up to date, which I wasn't, but the same note is there in V2.3 also.

I'm not sure if anything clears them; probably a PoR or the module reset of the whole PIO unit will do it, but I haven't tested it. Certainly I've often set X or Y in just the way you are planning to and never run into any difficulty.

Eric Buddington
Posts: 15
Joined: Mon May 03, 2021 1:53 pm

Re: When are PIO X/Y registers reset?

Wed Feb 14, 2024 4:15 pm

Thank you! I was indeed looking at an old version of the document.

Return to “General”