May be of interest?joan wrote:I'm afraid that means there has been another change.tvjon wrote:paddr=3f000000, baddr=C0000000
DMA is not working as it used to work.
http://infocenter.arm.com/help/index.js ... index.html
May be of interest?joan wrote:I'm afraid that means there has been another change.tvjon wrote:paddr=3f000000, baddr=C0000000
DMA is not working as it used to work.
I don't believe there's any licensing issue. I believe a half decent jit outperforms Jazelle, so no one supports Jazelle.jamesh wrote:Ref: Jazelle on Pi1, afaik, this is not enabled, and therefore unused. I think its a licensing issue rather than anything technical, but not sure.
jdb wrote: Single-threaded compute performance for tight loops (i.e. C or assembly routines) would be 1.8-2x faster. Compute performance for stuff with a larger memory footprint (interpreted languages like Java, Javascript, Ruby/Python) will benefit proportionally more due to the L2 cache.
This is the reason I have not released a new RPi.GPIO yet. I've not had time to investigate yet. Has anyone got any ideas?guzunty wrote:I am seeing a difference in behaviour of usleep between a B+ and Pi2.
Using a bitscope on non pi host I see 1ms on B+ but around 3ms on Pi2.
This is with a call to usleep(1000).
Has anyone else seen this or have I missed something?
[EDIT] Correction, I see 1ms on B+ and 28ms(!) on Pi2.
The main reason is that Cortex A7s have dual-issue instruction parallelism - Superscalar execution (but still in-order execution). Two instructions can be executed per clock cycle as long as there are no register or load/store dependencies on the preceeding instruction(s). Compilers targeting the core know this and optimise instruction scheduling to a certain extent. This plus the clock speed differential gives you ~2x for single-threaded and tight loops.solar3000 wrote:jdb wrote: Single-threaded compute performance for tight loops (i.e. C or assembly routines) would be 1.8-2x faster. Compute performance for stuff with a larger memory footprint (interpreted languages like Java, Javascript, Ruby/Python) will benefit proportionally more due to the L2 cache.
How do you get those numbers? 700MHz vs 900MHz isn't that different. What else would be making single threads go 2x?
I didn't start any threads myself. I used Gert and Doms demo program here:RaTTuS wrote:thread locking via different CPU cores ?
We moved both Pi1 and Pi2 to a 3.18 kernel base. There's nothing telling in the kernel configs between each platform that would result in timer discrepancies.guzunty wrote:I didn't start any threads myself. I used Gert and Doms demo program here:RaTTuS wrote:thread locking via different CPU cores ?
http://elinux.org/RPi_Low-level_peripherals#C_2
to make the measurements.
I just changed the sleep(1) to usleep(1000) and modified for the new peripheral base address.
Of course, something else could be contending for the GPIO or the timer.
Run web videos using the GPU (either with epiphany/kweb3 using gstreamer-1.0 or with kweb(3) + omxplayer(GUI)). They will play with full speed (and even full screen with the second solution). That works on all Pis. I don't believe, that the ARM7 can decode them by software alone.solar3000 wrote:So far no one has asked about youtube.
Pis A/B run youtube at one frame every 60 seconds.
How does pi 2 do?
dom wrote:I don't believe there's any licensing issue. I believe a half decent jit outperforms Jazelle, so no one supports Jazelle.jamesh wrote:Ref: Jazelle on Pi1, afaik, this is not enabled, and therefore unused. I think its a licensing issue rather than anything technical, but not sure.
That is also the answer I received way back in 2012 when I asked about an optimised JVM.Wikipedia wrote:The published specifications are very incomplete, being only sufficient for writing operating system code that can support a JVM that uses Jazelle[citation needed]. The declared intent is that only the JVM software needs to (or is allowed to) depend on the hardware interface details. This tight binding facilitates that the hardware and JVM can evolve together without affecting other software. In effect, this gives ARM Holdings considerable control over which JVMs are able to exploit Jazelle[citation needed]. It also prevents open source JVMs from using Jazelle. These issues do not apply to the ARMv7 ThumbEE environment, the nominal successor to Jazelle DBX.
ARM wrote: Jazelle v1 Architecture Reference Manual
This is a placeholder for a restricted document that is not available from this site. Please contact ARM for more information.
gkreidl wrote:Run web videos using the GPU (either with epiphany/kweb3 using gstreamer-1.0 or with kweb(3) + omxplayer(GUI)). They will play with full speed (and even full screen with the second solution). That works on all Pis. I don't believe, that the ARM7 can decode them by software alone.solar3000 wrote:So far no one has asked about youtube.
Pis A/B run youtube at one frame every 60 seconds.
How does pi 2 do?
Code: Select all
#include <unistd.h>
int main()
{
int x = 0;
for(x = 0; x < 1000; x++){
usleep(1000);
}
}
Code: Select all
pi@raspberrypi ~ $ time ./a.out
real 0m20.094s
user 0m0.000s
sys 0m0.020s
Code: Select all
pi@raspberrypi ~ $ time ./a.out
real 0m1.095s
user 0m0.000s
sys 0m0.020s
It's a bitfield that contains more information such as memory amount, processor, Pi model, manufacturer and revision.Leopold wrote:What is the meaning of the Revision shown in /proc/cpuinfo? For past models the final four hex digits were the revision number as indicated at http://elinux.org/RPi_HardwareHistory#B ... on_History but for the 2B it seems there is now more to it?
No flash video (except with the help of youtube-dl). HTML5 video should profit from the better CPU (often still a bit shaky in the browser right now), but only in a browser that uses GPU HW acceleration (epiphany/kweb3).solar3000 wrote: yes, I've run youtube and youtube-dl.
I meant in a browser without special tools, just flash or html5.
Leopold wrote:What is the meaning of the Revision shown in /proc/cpuinfo? For past models the final four hex digits were the revision number as indicated at http://elinux.org/RPi_HardwareHistory#B ... on_History but for the 2B it seems there is now more to it?
Code: Select all
32 bits
NEW 23: will be 1 for the new scheme, 0 for the old scheme
MEMSIZE 20: 0=256M 1=512M 2=1G
MANUFACTURER 16: 0=SONY 1=EGOMAN
PROCESSOR 12: 0=2835 1=2836
TYPE 04: 0=MODELA 1=MODELB 2=MODELA+ 3=MODELB+ 4=Pi2 MODEL B 5=ALPHA 6=CM
REV 00: 0=REV0 1=REV1 2=REV2
Yes, but don't blame me if it doesn'tpi-man-uk wrote:Will it work?
O_Ogadgetoid wrote: And when timed:Same SD card placed in a +B:Code: Select all
pi@raspberrypi ~ $ time ./a.out real 0m20.094s user 0m0.000s sys 0m0.020s
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pi@raspberrypi ~ $ time ./a.out real 0m1.095s user 0m0.000s sys 0m0.020s
ok thanks, I like your answer, I'll go for it. Then I need to swap out all my other Pi with Pi2! (mostly openelec) now I have found the promised land I can't sleep at night with the old model, need lots of 2amp PSUs and new cases also, as well as microSD cards... oh gawd...DirkS wrote:Yes, but don't blame me if it doesn'tpi-man-uk wrote:Will it work?
Did we mention it was faster?pattagghiu wrote:O_Ogadgetoid wrote: And when timed:Same SD card placed in a +B:Code: Select all
pi@raspberrypi ~ $ time ./a.out real 0m20.094s user 0m0.000s sys 0m0.020s
Code: Select all
pi@raspberrypi ~ $ time ./a.out real 0m1.095s user 0m0.000s sys 0m0.020s