bdg2 wrote: ↑Thu Jul 04, 2019 5:55 pm
How can a microSD card possibly have wear levelling?
Surely in an SSD with wear leveling the mapping table needs to be in RAM and there needs to be a bank of capacitors so that when the power goes off the processor in the SSD still has time to save the RAM to flash. If the table was just in flash and not held in RAM during operation then nothing would be achieved since it would just mean the flash that holds the table would wear out quickly and the life of the device would still be short.
It's offtopic; but, I will try a short answer.
I have read about WL in 2008, so my knowledges are outdated, and things are now much more powerfull than then.
But, already in that time, there were at least 5 completely different technologies; and 3 of them were already dedicated to SD cards (and 2 were possible only in larger SSDs).
One proof: go on Sandisk website, and, either read their web pages, or start a chat with the tech support. Since at least 2013, all their cards are certified to include WL.
How ? Let's make things simple: chips need to store a table to convert logical sectors into physical NAND gates. This allocation table is a huge mess, and needs to be stored. It's critical, but, much smaller than the data sectors; so, this table can be stored in a more reliable kind of gates (using larger transistors, less susceptible to aging). Considering modern technology, SD cards physically have plenty room for some RAM and a small power capacitor; so, it can be possible to store frequent modifications in RAM, and commit changes to long term storage only at unplug time. Also, keep in mind that SRAM can be certified 10 years (but are susceptible to cosmic rays, much more than other kings of memory).
There also are several different kinds of algorythm to handle that conversion table; the linear ones (which look like FAT32) are crappy but easy to implement. More complex ones are subbecjt to expensive patents, and involve algorythms similar to MD5 (a small seed and a medium algorythm are used to generate a long list of non consecutive numbers; but in the case of WL, unlike MD5 and GSM requirements, you need to generate numbers only once; the algo is similar to the onces used in GSM or Rolling Codes, except each output number exists only once in the output sequence). The aim is to have a bijection between the logical sectors, and the physical NANDs, where two consecutive logical sectors are NOT stored on adjascent NANDs. Because corruption is often located on a specific place of the chip, spreading a logical block all over the chip increases the chance to rebuild the user data (using CRC) when corruption of one block is detected.
Underneath this, good manufacturers may add a second translation layer to remap dead NANDs.
You also need a third mapping layer so that consecutive writes (in time) of the same logical block will not burn always the same NANDs.
SDs usually have 20 to 40% hidden gates; while SSDs have from 60 to 300%. Cheap SSDs may have less than 5%; or even down to 0% (some even sell 4GB chips under a 32GB packaging).
Even if SDs have less hidden blocks, and weaker processing power, they share large lines of concepts with SSD. But to be able to perform WL with a weaker computing unit, they have to work harder on the math side. IE, SDs are less sensible to free space ratio than SSDs.
